getting close to done

1 files changed, 84 insertions, 143 deletions

diff --git a/compiler_and_linker/unsorted/InstrSelection.c b/compiler_and_linker/unsorted/InstrSelection.c
index ac60baf..1916711 100644
--- a/compiler_and_linker/unsorted/InstrSelection.c
+++ b/compiler_and_linker/unsorted/InstrSelection.c
@@ -4,20 +4,20 @@
 #include "compiler/CMachine.h"
 #include "compiler/CParser.h"
 #include "compiler/CodeGen.h"
+#include "compiler/CompilerTools.h"
+#include "compiler/FunctionCalls.h"
+#include "compiler/Intrinsics.h"
 #include "compiler/Operands.h"
 #include "compiler/PCode.h"
 #include "compiler/PCodeInfo.h"
 #include "compiler/PCodeUtilities.h"
 #include "compiler/RegisterInfo.h"
+#include "compiler/StructMoves.h"
 #include "compiler/TOC.h"
-#include "compiler/CompilerTools.h"
 #include "compiler/enode.h"
 #include "compiler/objects.h"
 #include "compiler/types.h"
 
-// TODO: move me
-extern void move_block(Operand *, Operand *, SInt32, SInt32);
-
 PrecomputedOperand *precomputedoperands;
 void (*cgdispatch[MAXEXPR + 1])(ENode *, short, short, Operand *);
 
@@ -103,8 +103,7 @@ void gen_DEFINE(ENode *expr, short outputReg, short outputRegHi, Operand *output
 
 void gen_REUSE(ENode *expr, short outputReg, short outputRegHi, Operand *output) {
     ENode *inner = expr->data.monadic;
-#line 250
-    CError_ASSERT(ENODE_IS(inner, EDEFINE));
+    CError_ASSERT(250, ENODE_IS(inner, EDEFINE));
     gen_DEFINE(inner, outputReg, outputRegHi, output);
 }
 
@@ -250,8 +249,7 @@ void gen_INDIRECT(ENode *expr, short outputReg, short outputRegHi, Operand *outp
                 output->optype = OpndType_CRField;
                 break;
             default:
-#line 456
-                CError_FATAL();
+                CError_FATAL(456);
         }
         output->reg = vi->reg;
         output->object = NULL;
@@ -386,8 +384,7 @@ void gen_FORCELOAD(ENode *expr, short outputReg, short outputRegHi, Operand *out
         else
             ENSURE_GPR(output, inner->rtype, outputReg);
     } else if (!IS_TYPE_VOID(inner->rtype)) {
-#line 681
-        CError_FATAL();
+        CError_FATAL(681);
     }
 }
 
@@ -1114,8 +1111,7 @@ void gen_ASS(ENode *expr, short outputReg, short outputRegHi, Operand *output) {
         if (ENODE_IS(left, EINDIRECT)) {
             left = left->data.monadic;
         } else {
-#line 1759
-            CError_FATAL();
+            CError_FATAL(1759);
         }
         right = expr->data.cond.expr2;
     } else {
@@ -1149,8 +1145,7 @@ void gen_ASS(ENode *expr, short outputReg, short outputRegHi, Operand *output) {
                 output->optype = OpndType_VR;
                 break;
             default:
-#line 1810
-                CError_FATAL();
+                CError_FATAL(1810);
         }
         if (opright.reg != vi->reg) {
             PCodeArg a, b;
@@ -1382,14 +1377,12 @@ void gen_TYPCON(ENode *expr, short outputReg, short outputRegHi, Operand *output
     } else if (srctype->size == dsttype->size) {
         GEN_NODE_TO_REG(inner, outputReg, 0, output);
     } else {
-#line 2224
-        CError_FATAL();
+        CError_FATAL(2224);
     }
 }
 
 void gen_BITFIELD(ENode *expr, short outputReg, short outputRegHi, Operand *output) {
-#line 2238
-    CError_FATAL();
+    CError_FATAL(2238);
 }
 
 void gen_INTCONST(ENode *expr, short outputReg, short outputRegHi, Operand *output) {
@@ -1403,13 +1396,11 @@ void gen_INTCONST(ENode *expr, short outputReg, short outputRegHi, Operand *outp
 }
 
 void gen_FLOATCONST(ENode *expr, short outputReg, short outputRegHi, Operand *output) {
-#line 2294
-    CError_FATAL();
+    CError_FATAL(2294);
 }
 
 void gen_STRINGCONST(ENode *expr, short outputReg, short outputRegHi, Operand *output) {
-#line 2308
-    CError_FATAL();
+    CError_FATAL(2308);
 }
 
 static Boolean COND_is_ABS_MatchNodes(ENode *cond, ENode *expr1, ENode *expr2) {
@@ -1619,6 +1610,8 @@ void gen_COND(ENode *expr, short outputReg, short outputRegHi, Operand *output)
         Boolean flag;
         Operand op;
         int fneg_reg;
+        int fneg_reg2;
+        int fneg_reg3;
         int fsel_reg;
         int final_reg;
 
@@ -1648,8 +1641,7 @@ void gen_COND(ENode *expr, short outputReg, short outputRegHi, Operand *output)
                 right = tmp;
                 break;
             default:
-#line 2780
-                CError_FATAL();
+                CError_FATAL(2780);
         }
 
         if (ENODE_IS(left, EFLOATCONST) && CMach_FloatIsZero(left->data.floatval)) {
@@ -1680,12 +1672,12 @@ void gen_COND(ENode *expr, short outputReg, short outputRegHi, Operand *output)
                     GEN_NODE_TO_FPR(expr1, &op1, expr1->rtype, 0);
                     GEN_NODE_TO_FPR(expr2, &op2, expr2->rtype, 0);
 
-                    fneg_reg = ALLOC_FPR();
-                    emitpcode(PC_FNEG, fneg_reg, op.reg);
+                    fneg_reg2 = ALLOC_FPR();
+                    emitpcode(PC_FNEG, fneg_reg2, op.reg);
                     fsel_reg = ALLOC_FPR();
                     emitpcode(PC_FSEL, fsel_reg, op.reg, op1.reg, op2.reg);
                     final_reg = outputReg ? outputReg : ALLOC_FPR();
-                    emitpcode(PC_FSEL, final_reg, fneg_reg, fsel_reg, op2.reg);
+                    emitpcode(PC_FSEL, final_reg, fneg_reg2, fsel_reg, op2.reg);
                 }
                 break;
             case ELESS:
@@ -1695,18 +1687,17 @@ void gen_COND(ENode *expr, short outputReg, short outputRegHi, Operand *output)
                 GEN_NODE_TO_FPR(expr1, &op1, expr1->rtype, 0);
                 GEN_NODE_TO_FPR(expr2, &op2, expr2->rtype, 0);
 
-                fneg_reg = op.reg;
+                fneg_reg3 = op.reg;
                 if (flag) {
-                    fneg_reg = ALLOC_FPR();
-                    emitpcode(PC_FNEG, fneg_reg, op.reg);
+                    fneg_reg3 = ALLOC_FPR();
+                    emitpcode(PC_FNEG, fneg_reg3, op.reg);
                 }
 
                 final_reg = outputReg ? outputReg : ALLOC_FPR();
-                emitpcode(PC_FSEL, final_reg, fneg_reg, op1.reg, op2.reg);
+                emitpcode(PC_FSEL, final_reg, fneg_reg3, op1.reg, op2.reg);
                 break;
             default:
-#line 2862
-                CError_FATAL();
+                CError_FATAL(2862);
         }
 
         output->optype = OpndType_FPR;
@@ -1814,8 +1805,7 @@ void gen_COND(ENode *expr, short outputReg, short outputRegHi, Operand *output)
                         ENSURE_GPR(&op1, expr1->rtype, 0);
                         emitpcode(PC_AND, reg1, op1.reg, isel_op1.reg);
                     } else {
-#line 3119
-                        CError_FATAL();
+                        CError_FATAL(3119);
                     }
 
                     output->optype = OpndType_GPR;
@@ -1851,8 +1841,7 @@ void gen_COND(ENode *expr, short outputReg, short outputRegHi, Operand *output)
                     return;
 
                 default:
-#line 3168
-                    CError_FATAL();
+                    CError_FATAL(3168);
             }
         }
 
@@ -2157,9 +2146,8 @@ void gen_CONDASS(ENode *expr, short outputReg, short outputRegHi, Operand *outpu
         flag = 0;
         memclrw(&op, sizeof(Operand));
 
-#line 3704
-        CError_ASSERT(ENODE_IS(expr1, EINDIRECT));
-        CError_ASSERT(ENODE_IS(expr1->data.monadic, EOBJREF));
+        CError_ASSERT(3704, ENODE_IS(expr1, EINDIRECT));
+        CError_ASSERT(3705, ENODE_IS(expr1->data.monadic, EOBJREF));
 
         tmpreg = OBJECT_REG(expr1->data.monadic->data.objref);
         final_reg = outputReg ? tmpreg : ALLOC_FPR();
@@ -2187,8 +2175,7 @@ void gen_CONDASS(ENode *expr, short outputReg, short outputRegHi, Operand *outpu
                 flag2 = 0;
                 break;
             default:
-#line 3744
-                CError_FATAL();
+                CError_FATAL(3744);
         }
 
         if (ENODE_IS(left, EFLOATCONST) && CMach_FloatIsZero(left->data.floatval)) {
@@ -2251,8 +2238,7 @@ void gen_CONDASS(ENode *expr, short outputReg, short outputRegHi, Operand *outpu
                 emitpcode(PC_FSEL, final_reg, fneg_reg, op2.reg, op1.reg);
                 break;
             default:
-#line 2862
-                CError_FATAL();
+                CError_FATAL(2862);
         }
 
         if (op3.optype != OpndType_FPR)
@@ -2270,10 +2256,8 @@ void gen_CONDASS(ENode *expr, short outputReg, short outputRegHi, Operand *outpu
         ENode *abs_expr;
 
         memclrw(&isel_op, sizeof(Operand));
-#line 3966
-        CError_ASSERT(ENODE_IS(expr1, EINDIRECT));
-#line 3968
-        CError_ASSERT(ENODE_IS(expr1->data.monadic, EOBJREF));
+        CError_ASSERT(3966, ENODE_IS(expr1, EINDIRECT));
+        CError_ASSERT(3968, ENODE_IS(expr1->data.monadic, EOBJREF));
 
         if (CONDASS_is_ABS(cond, expr1, expr2)) {
             if (ENODE_IS(cond->data.diadic.left, EASS))
@@ -2282,14 +2266,12 @@ void gen_CONDASS(ENode *expr, short outputReg, short outputRegHi, Operand *outpu
                 GEN_NODE(cond->data.diadic.right, &isel_op);
 
             outputReg = OBJECT_REG(expr1->data.monadic->data.objref);
-#line 3979
-            CError_ASSERT(outputReg);
+            CError_ASSERT(3979, outputReg);
 
             GEN_NODE(expr1, &op1);
             op3 = op1;
 
-#line 3986
-            CError_ASSERT(op3.optype == OpndType_GPR && op3.reg == outputReg);
+            CError_ASSERT(3986, op3.optype == OpndType_GPR && op3.reg == outputReg);
 
             ENSURE_GPR(&op1, expr1->rtype, 0);
             if (expr1->rtype->size < 4)
@@ -2317,6 +2299,10 @@ void gen_CONDASS(ENode *expr, short outputReg, short outputRegHi, Operand *outpu
 }
 
 void gen_FUNCCALL(ENode *expr, short outputReg, short outputRegHi, Operand *output) {
+    if (is_intrinsic_function_call(expr))
+        call_intrinsic_function(expr, outputReg, output);
+    else
+        call_function(expr, output);
 }
 
 void gen_OBJREF(ENode *expr, short outputReg, short outputRegHi, Operand *output) {
@@ -2324,8 +2310,7 @@ void gen_OBJREF(ENode *expr, short outputReg, short outputRegHi, Operand *output
 }
 
 void gen_UNEXPECTED(ENode *expr, short outputReg, short outputRegHi, Operand *output) {
-#line 4160
-    CError_FATAL();
+    CError_FATAL(4160);
 }
 
 static int small(ENode *expr) {
@@ -2658,8 +2643,7 @@ void gen_LOGICAL(ENode *expr, short outputReg, short outputRegHi, Operand *outpu
 
             tmpreg1 = ALLOC_GPR();
             tmpreg2 = ALLOC_GPR();
-#line 4853
-            CError_ASSERT(output->optype == OpndType_GPR);
+            CError_ASSERT(4853, output->optype == OpndType_GPR);
 
             emitpcode(PC_CNTLZW, tmpreg2, output->reg);
             emitpcode(PC_RLWINM, tmpreg1, tmpreg2, 27, 5, 31);
@@ -2685,8 +2669,7 @@ void gen_LOGICAL(ENode *expr, short outputReg, short outputRegHi, Operand *outpu
 
             tmpreg1 = ALLOC_GPR();
             tmpreg2 = ALLOC_GPR();
-#line 4883
-            CError_ASSERT(output->optype == OpndType_GPR);
+            CError_ASSERT(4883, output->optype == OpndType_GPR);
 
             emitpcode(PC_CNTLZW, tmpreg2, output->reg);
             emitpcode(PC_RLWINM, tmpreg1, tmpreg2, 27, 5, 31);
@@ -2810,8 +2793,7 @@ void logical_expression(ENode *cond, PCodeLabel *if_true, PCodeLabel *if_false,
                 branch_conditional(op.reg, op.regOffset, 1, if_true);
             break;
         default:
-#line 5160
-            CError_FATAL();
+            CError_FATAL(5160);
     }
 }
 
@@ -2829,8 +2811,7 @@ static void logical_expression_nobranch(ENode *cond, Boolean invert, Operand *ou
         case ENOTEQU:
             if (invert) {
                 ENodeType nt = invert_relop(cond->type);
-#line 5190
-                CError_ASSERT(nt != cond->type);
+                CError_ASSERT(5190, nt != cond->type);
                 cond->type = nt;
             }
 
@@ -2841,8 +2822,7 @@ static void logical_expression_nobranch(ENode *cond, Boolean invert, Operand *ou
 
             break;
         default:
-#line 5206
-            CError_FATAL();
+            CError_FATAL(5206);
     }
 }
 
@@ -2999,8 +2979,7 @@ void gen_condition_gpr(ENode *cond, Operand *output, short outputReg) {
                                         pc->args[1].data.reg.reg,
                                         (r6 + r7 + 1) & 31, 31, 31);
                             } else {
-#line 5434
-                                CError_FATAL();
+                                CError_FATAL(5434);
                             }
                             output->optype = OpndType_GPR;
                             output->reg = reg;
@@ -3061,8 +3040,7 @@ void gen_condition_gpr(ENode *cond, Operand *output, short outputReg) {
                                         (r6 + r7 + 1) & 31, 31, 31);
                                 emitpcode(PC_XORI, reg, tmpreg, 1);
                             } else {
-#line 5503
-                                CError_FATAL();
+                                CError_FATAL(5503);
                             }
                             output->optype = OpndType_GPR;
                             output->reg = reg;
@@ -3265,8 +3243,7 @@ void gen_condition_gpr(ENode *cond, Operand *output, short outputReg) {
                 }
 
             default:
-#line 5777
-                CError_FATAL();
+                CError_FATAL(5777);
         }
     }
 
@@ -3589,8 +3566,7 @@ void I8_gen_ADD(ENode *expr, short outputReg, short outputRegHi, Operand *output
         case 1 + 8:
         case 2 + 8:
         case 4 + 8:
-#line 6933
-            CError_ASSERT(skipleft == 8);
+            CError_ASSERT(6933, skipleft == 8);
             if (!is_uns) {
                 tmpreg2 = ALLOC_GPR();
                 emitpcode(PC_SRAWI, tmpreg2, opright.reg, 31);
@@ -3612,8 +3588,7 @@ void I8_gen_ADD(ENode *expr, short outputReg, short outputRegHi, Operand *output
             emitpcode(PC_ADDE, regHi, opleft.regHi, opright.regHi);
             break;
         default:
-#line 6979
-            CError_FATAL();
+            CError_FATAL(6979);
     }
 
     output->optype = OpndType_GPRPair;
@@ -3745,8 +3720,7 @@ void I8_gen_SUB(ENode *expr, short outputReg, short outputRegHi, Operand *output
             emitpcode(PC_SUBFE, regHi, opright.regHi, opleft.regHi);
             break;
         default:
-#line 7211
-            CError_FATAL();
+            CError_FATAL(7211);
     }
 
     output->optype = OpndType_GPRPair;
@@ -3840,10 +3814,8 @@ int I8_log2n(UInt64 val) {
 }
 
 void I8_ShiftLeftImmediate(Operand opnd, SInt32 value, int is_unsigned, SInt32 size, short reg, short regHi) {
-    if (opnd.reg == reg || opnd.regHi == regHi || opnd.reg == regHi || opnd.regHi == reg) {
-#line 7703
-        CError_FATAL();
-    }
+    if (opnd.reg == reg || opnd.regHi == regHi || opnd.reg == regHi || opnd.regHi == reg)
+        CError_FATAL(7703);
 
     if (value < 32) {
         emitpcode(PC_RLWINM, reg, opnd.reg, value, 0, 31 - value);
@@ -3860,8 +3832,7 @@ void I8_ShiftLeftImmediate(Operand opnd, SInt32 value, int is_unsigned, SInt32 s
             emitpcode(PC_RLWINM, regHi, opnd.reg, value - 32, 0, 63 - value);
         emitpcode(PC_LI, reg, 0);
     } else {
-#line 7732
-        CError_FATAL();
+        CError_FATAL(7732);
     }
 }
 
@@ -3871,10 +3842,8 @@ void I8_ShiftRightImmediate(Operand opnd, SInt32 value, int is_unsigned, short r
     short tmpreg3;
     short tmpreg4;
 
-    if (opnd.reg == reg || opnd.regHi == regHi || opnd.reg == regHi || opnd.regHi == reg) {
-#line 7756
-        CError_FATAL();
-    }
+    if (opnd.reg == reg || opnd.regHi == regHi || opnd.reg == regHi || opnd.regHi == reg)
+        CError_FATAL(7756);
 
     if (value < 32) {
         emitpcode(PC_RLWINM, reg, opnd.reg, 32 - value, 0, 31);
@@ -3927,8 +3896,7 @@ void I8_ShiftRightImmediate(Operand opnd, SInt32 value, int is_unsigned, short r
             emitpcode(PC_SRAWI, regHi, opnd.regHi, 31);
         }
     } else {
-#line 7866
-        CError_FATAL();
+        CError_FATAL(7866);
     }
 }
 
@@ -3957,10 +3925,8 @@ void I8_gen_MUL(ENode *expr, short outputReg, short outputRegHi, Operand *output
     skipleft = GetSizeSkip(left);
     skipright = GetSizeSkip(right);
 
-    if (ENODE_IS(right, EINTCONST) && ENODE_IS(left, EINTCONST)) {
-#line 7900
-        CError_FATAL();
-    }
+    if (ENODE_IS(right, EINTCONST) && ENODE_IS(left, EINTCONST))
+        CError_FATAL(7900);
 
     if (ENODE_IS(left, EINTCONST))
         leftval = left->data.intval.lo + (((SInt64) ((skipleft < 8) ? 0 : left->data.intval.hi)) << 32);
@@ -4066,8 +4032,7 @@ void I8_gen_MUL(ENode *expr, short outputReg, short outputRegHi, Operand *output
             case 1 + 8:
             case 2 + 8:
             case 4 + 8:
-#line 8097
-                CError_ASSERT(skipleft == 8);
+                CError_ASSERT(8097, skipleft == 8);
                 if (ENODE_IS(left, EINTCONST) && FITS_IN_SHORT2(left->data.intval.lo) && left->data.intval.hi == 0) {
                     emitpcode(PC_MULLI, reg, opright.reg, LOW_PART(left->data.intval.lo));
                     if (is_uns)
@@ -4143,8 +4108,7 @@ void I8_gen_MUL(ENode *expr, short outputReg, short outputRegHi, Operand *output
                 }
                 break;
             default:
-#line 8218
-                CError_FATAL();
+                CError_FATAL(8218);
         }
     }
 
@@ -4206,12 +4170,10 @@ void I8_gen_ASS(ENode *expr, short outputReg, short outputRegHi, Operand *output
     type = expr->rtype;
     if (ENODE_IS(expr, ECONDASS)) {
         left = expr->data.cond.expr1;
-        if (ENODE_IS(left, EINDIRECT)) {
+        if (ENODE_IS(left, EINDIRECT))
             left = left->data.monadic;
-        } else {
-#line 8328
-            CError_FATAL();
-        }
+        else
+            CError_FATAL(8238);
         right = expr->data.cond.expr2;
     } else {
         left = expr->data.diadic.left;
@@ -4225,8 +4187,7 @@ void I8_gen_ASS(ENode *expr, short outputReg, short outputRegHi, Operand *output
         vi = Registers_GetVarInfo(left->data.objref);
         GEN_NODE_TO_REG(right, vi->reg, vi->regHi, &opright);
         if (vi->rclass != RegClass_GPR) {
-#line 8348
-            CError_FATAL();
+            CError_FATAL(8348);
         } else {
             coerce_to_register_pair(&opright, type, vi->reg, vi->regHi);
             *output = opright;
@@ -4239,8 +4200,7 @@ void I8_gen_ASS(ENode *expr, short outputReg, short outputRegHi, Operand *output
         coerce_to_register_pair(&opright, right->rtype, 0, 0);
 
         if (ENODE_IS(left, EBITFIELD)) {
-#line 8376
-            CError_FATAL();
+            CError_FATAL(8376);
         } else {
             GEN_NODE(left, &opleft);
             indirect(&opleft, left);
@@ -4286,8 +4246,7 @@ void I8_gen_POSTINCDEC(ENode *expr, short outputReg, short outputRegHi, Operand
         return;
     }
 
-#line 8446
-    CError_ASSERT(!ENODE_IS(inner, EBITFIELD));
+    CError_ASSERT(8446, !ENODE_IS(inner, EBITFIELD));
 
     GEN_NODE(inner, &op1);
     indirect(&op1, inner);
@@ -4329,8 +4288,7 @@ void I8_gen_INDIRECT(ENode *expr, short outputReg, short outputRegHi, Operand *o
                 output->optype = OpndType_FPR;
                 break;
             default:
-#line 8511
-                CError_FATAL();
+                CError_FATAL(8511);
         }
 
         output->reg = vi->reg;
@@ -4340,8 +4298,7 @@ void I8_gen_INDIRECT(ENode *expr, short outputReg, short outputRegHi, Operand *o
     }
 
     if (ENODE_IS(inner, EBITFIELD)) {
-#line 8529
-        CError_FATAL();
+        CError_FATAL(8529);
         return;
     }
 
@@ -4430,8 +4387,7 @@ void I8_gen_condition(ENode *cond, Operand *output, int write_to_gpr) {
         }
     }
 
-#line 8704
-    CError_ASSERT(opleft.optype == OpndType_GPRPair && opright.optype == OpndType_GPRPair);
+    CError_ASSERT(8704, opleft.optype == OpndType_GPRPair && opright.optype == OpndType_GPRPair);
 
     switch (cond->type) {
         case EEQU:
@@ -4525,8 +4481,7 @@ void I8_gen_condition(ENode *cond, Operand *output, int write_to_gpr) {
             }
             break;
         default:
-#line 8814
-            CError_FATAL();
+            CError_FATAL(8814);
     }
 }
 
@@ -4569,8 +4524,7 @@ void I8_gen_SHL_SHR(ENode *expr, short outputReg, short outputRegHi, Operand *ou
         opright.optype = OpndType_GPR;
     }
 
-#line 8890
-    CError_ASSERT(opleft.optype == OpndType_GPRPair && opright.optype == OpndType_GPR);
+    CError_ASSERT(8890, opleft.optype == OpndType_GPRPair && opright.optype == OpndType_GPR);
 
     if (opleft.regHi != high_reg)
         emitpcode(PC_MR, high_reg, opleft.regHi);
@@ -4587,8 +4541,7 @@ void I8_gen_SHL_SHR(ENode *expr, short outputReg, short outputRegHi, Operand *ou
     } else if (ENODE_IS(expr, ESHL)) {
         branch_subroutine(rt_shl2i, 0, used_regs);
     } else {
-#line 8909
-        CError_FATAL();
+        CError_FATAL(8909);
     }
 
     emitpcode(PC_MR, output->reg, low_reg);
@@ -4623,8 +4576,7 @@ void I8_gen_DIV_MOD(ENode *expr, short outputReg, short outputRegHi, Operand *ou
     if (ENODE_IS(right, EINTCONST))
         constval = (((SInt64) right->data.intval.hi) << 32) + right->data.intval.lo;
     if (ENODE_IS(right, EINTCONST) && ((shift = I8_log2n(constval)) > 0)) {
-#line 8976
-        CError_ASSERT(opleft.optype == OpndType_GPRPair);
+        CError_ASSERT(8976, opleft.optype == OpndType_GPRPair);
         if (ENODE_IS(expr, EDIV)) {
             I8_ShiftRightImmediate(opleft, shift, is_uns, output->reg, output->regHi, 1);
             if (!is_uns) {
@@ -4643,8 +4595,7 @@ void I8_gen_DIV_MOD(ENode *expr, short outputReg, short outputRegHi, Operand *ou
                     emitpcode(PC_RLWINM, output->regHi, opleft.regHi, 0, 32 - (shift - 32), 31);
                     emitpcode(PC_MR, output->reg, opleft.reg);
                 } else {
-#line 9018
-                    CError_FATAL();
+                    CError_FATAL(9018);
                 }
             } else {
                 short tmpreg1 = ALLOC_GPR();
@@ -4663,8 +4614,7 @@ void I8_gen_DIV_MOD(ENode *expr, short outputReg, short outputRegHi, Operand *ou
     GEN_NODE(right, &opright);
     coerce_to_register_pair(&opright, right->rtype, 0, 0);
 
-#line 9048
-    CError_ASSERT(opleft.optype == OpndType_GPRPair && opright.optype == OpndType_GPRPair);
+    CError_ASSERT(9048, opleft.optype == OpndType_GPRPair && opright.optype == OpndType_GPRPair);
 
     if (opleft.regHi != high_reg)
         emitpcode(PC_MR, high_reg, opleft.regHi);
@@ -4686,8 +4636,7 @@ void I8_gen_DIV_MOD(ENode *expr, short outputReg, short outputRegHi, Operand *ou
         else
             branch_subroutine(rt_mod2i, 0, used_regs);
     } else {
-#line 9074
-        CError_FATAL();
+        CError_FATAL(9074);
     }
 
     emitpcode(PC_MR, output->reg, low_reg);
@@ -4745,8 +4694,7 @@ void I8_gen_TYPCON(ENode *expr, short outputReg, short outputRegHi, Operand *out
         }
 
         if (srctype->size < dsttype->size) {
-#line 9171
-            CError_ASSERT(TYPE_IS_8BYTES(dsttype));
+            CError_ASSERT(9171, TYPE_IS_8BYTES(dsttype));
 
             GEN_NODE(inner, output);
             if (srctype->size < 4 &&
@@ -4769,8 +4717,7 @@ void I8_gen_TYPCON(ENode *expr, short outputReg, short outputRegHi, Operand *out
 
     if (IS_TYPE_POINTER(srctype)) {
         GEN_NODE_TO_REG(inner, outputReg, 0, output);
-#line 9200
-        CError_ASSERT(TYPE_IS_8BYTES(expr->rtype));
+        CError_ASSERT(9200, TYPE_IS_8BYTES(expr->rtype));
         GEN_NODE_TO_REG(inner, outputReg, 0, output);
 
         regHi = outputRegHi ? outputRegHi : ALLOC_GPR();
@@ -4790,8 +4737,7 @@ void I8_gen_TYPCON(ENode *expr, short outputReg, short outputRegHi, Operand *out
 
     if (IS_TYPE_FLOAT(srctype)) {
         if (IS_TYPE_FLOAT(dsttype)) {
-#line 9222
-            CError_FATAL();
+            CError_FATAL(9222);
             return;
         }
 
@@ -4816,14 +4762,12 @@ void I8_gen_TYPCON(ENode *expr, short outputReg, short outputRegHi, Operand *out
         if (TYPE_IS_8BYTES(expr->rtype) && dsttype->size == srctype->size) {
             coerce_to_register_pair(output, srctype, outputReg, outputRegHi);
         } else {
-#line 9256
-            CError_FATAL();
+            CError_FATAL(9256);
         }
         return;
     }
 
-#line 9261
-    CError_FATAL();
+    CError_FATAL(9261);
 }
 
 void gen_VECTOR128CONST(ENode *expr, short outputReg, short outputRegHi, Operand *output) {
@@ -4832,10 +4776,8 @@ void gen_VECTOR128CONST(ENode *expr, short outputReg, short outputRegHi, Operand
     COVCResult result;
 
     vr = outputReg ? outputReg : ALLOC_VR();
-    if (!canoptimizevectorconst(&expr->data.vector128val, expr->rtype, &result)) {
-#line 9282
-        CError_FATAL();
-    }
+    if (!canoptimizevectorconst(&expr->data.vector128val, expr->rtype, &result))
+        CError_FATAL(9282);
 
     if (result.op1 != -1) {
         emitpcode(result.op1, vr, result.arg);
@@ -4853,6 +4795,5 @@ void gen_VECTOR128CONST(ENode *expr, short outputReg, short outputRegHi, Operand
         return;
     }
 
-#line 9298
-    CError_FATAL();
+    CError_FATAL(9298);
 }